Logic networks using MOS technology are often formed with NAND gates, NOR gates and Inverter gates since these structures are easily implemented. A standard cell is simply a digital logic element made up of such gates. The standard cell performs a specified function and is laid out in a predefined fashion. A number of such cells are pre-laid out and made available in a library. FIG. 1 shows the circuit schematic of one such cell (a 2-input NAND gate) in CMOS technology. Using the standard cells in the library, a design is captured via schematic capture or Hardware Description Language HDL). Then through a delay versus area analysis, the overall logic implementation is optimized. The layout is then automatically placed and routed by CAD software. The layout is usually identifiable as rows of constant height blocks separated by rows of routing, as shown in FIG. 2.
The standard cell approach however, suffers from certain drawbacks:
(1) Power consumption: with every gate transition, power is consumed in charging or discharging the capacitive load at the output node of the gate. Every gate that makes a transition also draws crow-bar current (current drawn from the power supply terminal and into the ground terminal for a given period of time) which increases the overall power consumption. These two types of power consumption are commonly referred to as dynamic power consumption. Depending upon the size of transistors, capacitive loading at output nodes and the size of the particular circuit, dynamic power consumption may be quite large. PA1 (2) Gate capacitance: because of the high capacitance associated with the gates of PMOS and NMOS transistors, and the requirement of PMOS to NMOS transistor size ratio of 2 to 1 in gate design, CMOS gates typically have large input capacitance and consume large portions of silicon area. The large input capacitance hinders propagation delays, and at times requires a buffering scheme wherein a chain of gates are needed to effectively drive a given node. PA1 (3) Multiple gate levels: implementing complex gates using the standard cell library approach typically requires multiple levels of logic gates, which adversely impacts area and power consumption as well as propagation delays. PA1 (4) Large cell library: the standard cell approach requires a library of cells which, depending upon the types of designs intended, may require a large number of cells. Every cell in the library needs to be designed and characterized, and as such development of large cell libraries are quite costly. Transferring cell libraries across generations of technology is also quite costly since redesign and recharacterization of all the cells are often required. PA1 (5) Inefficient synthesis: the standard cell approach is not synthesis efficient for a number of reasons. First, synthesis tools lack the sophistication needed to achieve optimal area in all cases. For example, in mapping a complex equation, a portion of which may efficiently be mapped into a complex cell, the synthesis tools are often incapable of recognizing such opportunities. Instead, the complex equation is inefficiently mapped into an excessive number of cells. Second, every cell library has a finite number of cells, and is designed for a particular size design. For example, for implementation of complex VLSI designs a larger cell library is needed as compared to simpler SSI designs. Within each area of design however, the cell library provides only a limited set of cells, which can at times lead to inefficient implementation of a design, e.g. two or more cells used where a single more compact cell could be used. Third, for larger cell libraries, due to the large number of cells that need to be analyzed, the compute time in implementing any logic function is quite long. PA1 (6) Low granularity: the cells in the cell library are typically 2 to 6-input single-output logic gates. To implement large logic functions using such cells, requires a significant number of cells, which results in more logic stages and a significant number of interconnections and buffering. PA1 (7) Interconnect delay: the performance of a design based on the standard cell approach is typically limited by the interconnect propagation delays. This is due to the large number of interconnections caused by the low granularity of the standard cells, as well as the fact that no particular structure is provided for the place and route tool in routing such critical signals as Clock and Scan. PA1 (i) sharing of resources such as the control input buffer section; PA1 (ii) an efficient integration of the Pass Transistor Logic technology into each MTL module; and PA1 (iii) use of three variables in a highly automated design procedure wherein each variable places a different constraint on the MTL modules. PA1 (1) A control input buffer section which has a number of input terminals for receiving control input signals, and a number of output terminals for providing the true and complement signals of the control input signals; PA1 (2) An output stage section which has a number of input terminals and a number of output terminals; PA1 (3) A matrix array section, which implements logic functions using Pass Transistor Logic technology. The matrix array section is made up of a number of pass-groups, wherein each pass-group includes a number of rows of pass transistors. In each pass-group one end of the rows receive a set of pass input signals via a first set of input terminals, and the other end of the rows is shorted together and connected to one of the input terminals of the output stage section. The gate terminals of the pass transistors in the pass-groups receive the true and complement signals of the control input signals from the control input buffer section. PA1 (i) A pass input buffer section which receives pass input signals and provides true and complement signals of the pass input signals, wherein the true and complement signals are received by the first set of input terminals of the matrix array section; PA1 (ii) A driver circuit, wherein the strength of the driver circuit is adjusted based on the capacitive load driven by the driver circuit; and PA1 (iii) Any synchronous circuits such as flip-flop registers and latch circuits. PA1 (a) The design is entered using a design entry tool. PA1 (b) Using a synthesis program, a number of optimized boolean expressions and sequential elements are generated from the entered design. Prior to execution of the synthesis program, the synthesis program is provided a value for the third variable described above. The synthesis program uses a synthesis library in generating the boolean expressions. The synthesis library includes basic primitives which are function-independent. PA1 (c) The boolean expressions are mapped into a circuit of single-output Matrix Transistor Logic (MTL) modules. Each single-output MTL module implements one boolean expression using Pass Transistor Logic technology. Each single-output MTL module receives control input signals corresponding to the literals in each boolean expression; PA1 (d) Using a packing algorithm, the single-output MTL modules are packed into a number of multiple-output MTL modules. The packing algorithm receives a value for each of the first and second variables described above. The execution of the packing algorithm results in placing single-output MTL modules with the most number of common control input signals together in one multiple-output MTL module within the limitations provided by the first and second variables; PA1 (e) Using an algorithm, the layout representation of each of the multiple-output MTL modules is constructed. The algorithm selects appropriate layout primitives from a library which includes a set of basic layout primitives; and PA1 (f) The multiple-output MTL modules are placed and interconnected using a place and route program.
The pass transistor is another common MOS structure, which over the years has gained significant popularity as another means of implementing logic gates. This has led to the development of what is known in the art as the Pass Transistor Logic (PTL) technology (see the textbook by C. A. Mead and L. A. Conway, Introduction to VLSI Systems, Reading, Mass.: Addison Wesley, 1980.
The PTL approach possesses a number of beneficial characteristics making it a more attractive approach than the conventional CMOS logic gate approach. The PTL approach maximizes the regularity of the resulting logic circuitry, and results in significant topological, power and speed advantages over the classical logic design methods. First, the pass transistor dissipates no significant steady state power. Second, arrays of pass transistors form structures of regular topology, often consuming less area for a given logical function than equivalent conventional logic gates. Third, combinational logic formed with pass transistors often reduces the signal propagation delay through a network.
One disadvantage of the PTL approach is that the voltage level of the logic high signal is degraded due to the characteristics of the field effect transistor used as a pass transistor. However, this can be overcome by simple signal-restoring techniques (see the article by Alex Shubat et. al., Differential Pass Transistor Logic in CMOS Technology, Electronics Letters 13, Vol. 22 No. 6, PP. 294-295, March 1986). Also, after passing a logic high level through one pass transistor, no significant further degradation of the high voltage level occurs when the signal is passed through additional pass transistors, assuming no pass transistor control gate is driven by the output of another pass transistor.
The use of the PTL approach has generally been limited to implementation of relatively small logic circuits, such as the priority encoder circuit disclosed in U.S. Pat. No. 4,622,648 to S. R. Whitaker, or the adder circuit in U.S. Pat. No. 5,148,387 patent to K. Yano et. al. The PTL approach has also been used to implement the cells for a standard cell library as disclosed in the article by K. Yano et. al., Top-Down Pass-Transistor Logic Design, IEEE JSSC vol. 31, no. 5, June 1996. Although the approach disclosed in the K. Yano et. al. article exploits some of the basic advantages of the PTL technology, Yano's approach suffers from the same general drawbacks associated with the conventional standard cell library approach described above.
The advantages of the PTL approach have not been fully exploited in implementation of large scale logic circuits primarily due to lack of a design methodology in which the PTL technology could be integrated in an efficient and automated fashion.